edalize package

Submodules

edalize.edatool module

class edalize.edatool.Edatool(edam=None, work_root=None, eda_api=None, verbose=True)[source]

Bases: object

build()[source]
build_main(target=None)[source]
build_post()[source]
build_pre()[source]
configure(args=[])[source]
configure_main()[source]
configure_post()[source]
configure_pre()[source]
classmethod get_doc(api_ver)[source]
parse_args(args, paramtypes)[source]
render_template(template_file, target_file, template_vars={})[source]

Render a Jinja2 template for the backend.

The template file is expected in the directory templates/BACKEND_NAME.

run(args={})[source]
run_main()[source]
run_post()[source]
run_pre(args=None)[source]
set_default_target(target)[source]
class edalize.edatool.FileAction(option_strings, dest, nargs=None, const=None, default=None, type=None, choices=None, required=False, help=None, metavar=None)[source]

Bases: Action

edalize.edatool.get_edatool(name)[source]
edalize.edatool.get_edatools()[source]
edalize.edatool.jinja_filter_param_value_str(value, str_quote_style='', bool_is_str=False)[source]

Convert a parameter value to string suitable to be passed to an EDA tool.

Rules:

  • Booleans are represented as 0/1 or “true”/”false” depending on the bool_is_str argument

  • Strings are either passed through or enclosed in the characters specified in str_quote_style (e.g. ‘”’ or ‘"’)

  • Everything else (including int, float, etc.) are converted using the str() function.

edalize.edatool.subprocess_run_3_9(*popenargs, input=None, capture_output=False, timeout=None, check=False, **kwargs)[source]
edalize.edatool.walk_tool_packages()[source]

edalize.ghdl module

class edalize.ghdl.Ghdl(edam=None, work_root=None, eda_api=None, verbose=True)[source]

Bases: Edatool

argtypes = ['vlogparam', 'generic']
configure_main()[source]
classmethod get_doc(api_ver)[source]
run_main()[source]

edalize.icarus module

class edalize.icarus.Icarus(edam=None, work_root=None, eda_api=None, verbose=True)[source]

Bases: Edatool

argtypes = ['plusarg', 'vlogdefine', 'vlogparam']
configure_main()[source]
classmethod get_doc(api_ver)[source]
run_main()[source]

edalize.icestorm module

class edalize.icestorm.Icestorm(edam=None, work_root=None, eda_api=None, verbose=True)[source]

Bases: Edatool

argtypes = ['vlogdefine', 'vlogparam']
build_main()[source]
build_post()[source]
build_pre()[source]
configure_main()[source]
classmethod get_doc(api_ver)[source]

edalize.ise module

class edalize.ise.Ise(edam=None, work_root=None, eda_api=None, verbose=True)[source]

Bases: Edatool

MAKEFILE_TEMPLATE = '#Auto generated by Edalize\ninclude config.mk\n\nall: $(TOPLEVEL).bit\n\n$(TOPLEVEL).bit:  $(NAME)_run.tcl $(NAME).xise\n\t$(EDALIZE_LAUNCHER) xtclsh $^\n\n$(NAME).xise: $(NAME).tcl\n\t$(EDALIZE_LAUNCHER) xtclsh $<\n'
PGM_FILE_TEMPLATE = '\n# Batch script for programming the device using a JTAG interface.\n# Used with:\n# $ impact -batch {pgm_file}\n\nsetMode -bscan\nsetCable -port auto\nidentify\nassignFile -p {board_device_index} -file {bit_file}\nprogram -p {board_device_index}\nsaveCDF -file {cdf_file}\nquit\n'
TCL_FILE_TEMPLATE = '#Auto generated by Edalize\nproc project_new_exist_ok name {{\n    if {{ [catch  {{ project new $name }}] }} {{\n        project open $name\n    }}\n}}\n\nproc xfile_add_exist_ok name {{\n    if {{ [catch {{ xfile get [file tail $name] name }}] }} {{\n        xfile add $name\n    }}\n}}\n\nproject_new_exist_ok {design}\nproject set family "{family}"\nproject set device {device}\nproject set package {package}\nproject set speed {speed}\nproject set "Generate Detailed MAP Report" true\n'
TCL_RUN_FILE_TEMPLATE = '#Auto generated by Edalize\nproject open $::argv\nprocess run "Generate Programming File"\n'
argtypes = ['vlogdefine', 'vlogparam', 'generic']
configure_main()[source]
classmethod get_doc(api_ver)[source]
run_main()[source]

edalize.isim module

class edalize.isim.Isim(edam=None, work_root=None, eda_api=None, verbose=True)[source]

Bases: Edatool

CONFIG_MK_TEMPLATE = '#Auto generated by Edalize\nTARGET        = {target}\nTOPLEVEL      = {toplevel}\n\nVLOG_DEFINES  = {vlog_defines}\nVLOG_INCLUDES = {vlog_includes}\nVLOG_PARAMS   = {vlog_params}\n\nFUSE_OPTIONS  =\t{fuse_options}\nISIM_OPTIONS  =\t{isim_options}\n\nEXTRA_OPTIONS ?= {extra_options}\n'
MAKEFILE_TEMPLATE = '#Auto generated by Edalize\ninclude config.mk\n\nall: $(TARGET)\n\n$(TARGET):\n\tfuse $(TOPLEVEL) -prj $(TARGET).prj -o $(TARGET) $(VLOG_DEFINES) $(VLOG_INCLUDES) $(VLOG_PARAMS) $(FUSE_OPTIONS)\n\nrun: $(TARGET)\n\t./$(TARGET) -tclbatch run_$(TARGET).tcl $(ISIM_OPTIONS) $(EXTRA_OPTIONS)\n\nrun-gui: $(TARGET)\n\t./$(TARGET) -gui $(ISIM_OPTIONS) $(EXTRA_OPTIONS)\n'
RUN_TCL_TEMPLATE = '#Auto generated by Edalize\nwave log -r /\nrun all\nquit\n'
argtypes = ['plusarg', 'vlogdefine', 'vlogparam']
configure_main()[source]
classmethod get_doc(api_ver)[source]
run_main()[source]

edalize.modelsim module

class edalize.modelsim.Modelsim(edam=None, work_root=None, eda_api=None, verbose=True)[source]

Bases: Edatool

argtypes = ['plusarg', 'vlogdefine', 'vlogparam', 'generic']
configure_main()[source]
classmethod get_doc(api_ver)[source]
run_main()[source]

edalize.openfpga module

class edalize.openfpga.Openfpga(edam=None, work_root=None, eda_api=None, verbose=False)[source]

Bases: Edatool

This calls the parent constructor, but also identifies whether the current system has correctly set the following environment variables:

argtypes = ['plusarg', 'vlogdefine', 'vlogparam']
build_main()[source]
configure_main()[source]

Configuration is the first phase of the build.

This writes an OpenFPGA task file for SOFA/SOFA+ architectures, which will generate the according OpenFPGA flow. It first collects all verilog sources, top_module and then writes them into the task file.

Note: OpenFPGA flow may uses Yosys/VPR backend for Synthesis and P&R, respectively.

classmethod get_doc(api_ver)[source]
run_main()[source]

Run the FPGA simulation.

edalize.openfpga.logger = <Logger edalize.openfpga (WARNING)>

OpenFPGA Flow Backend.

A core (usually the system core) can add the following files:

  • Benchmark RTL sources (Yosys supports only Verilog file type) and module name

  • The target FPGA architecture name, made with OpenFPGA fabric flow (SOFA,…)

  • Source the required environment variables: OPENFPGA_PATH, SOFA_PATH

  • Optional parameters: task options (’–debug’, …)

edalize.quartus module

class edalize.quartus.Quartus(edam=None, work_root=None, eda_api=None, verbose=False)[source]

Bases: Edatool

Initial setup of the class.

This calls the parent constructor, but also identifies whether the current system is using a Standard or Pro edition of Quartus.

argtypes = ['vlogdefine', 'vlogparam', 'generic']
build_main()[source]
configure_main()[source]

Configuration is the first phase of the build.

This writes the project TCL files and Makefile. It first collects all sources, IPs and constraints and then writes them to the TCL file along with the build steps.

file_type(f)[source]
classmethod get_doc(api_ver)[source]
isPro = False
makefile_template = {False: 'quartus-std-makefile.j2', True: 'quartus-pro-makefile.j2'}
qsys_file_filter(f)[source]
run_main()[source]

Program the FPGA.

src_file_filter(f)[source]

edalize.rivierapro module

class edalize.rivierapro.Rivierapro(edam=None, work_root=None, eda_api=None, verbose=True)[source]

Bases: Edatool

argtypes = ['plusarg', 'vlogdefine', 'vlogparam']
build_main()[source]
build_pre()[source]
configure_main()[source]
classmethod get_doc(api_ver)[source]
run_main()[source]

edalize.symbiyosys module

class edalize.symbiyosys.Symbiyosys(edam=None, work_root=None, eda_api=None, verbose=True)[source]

Bases: Edatool

argtypes = ['vlogdefine', 'vlogparam']
build_main()[source]
configure_main()[source]
static get_doc(api_ver)[source]
run_main()[source]
tool_options = {'lists': {'tasknames': 'String'}}

edalize.spyglass module

class edalize.spyglass.Spyglass(edam=None, work_root=None, eda_api=None, verbose=True)[source]

Bases: Edatool

argtypes = ['vlogdefine', 'vlogparam']
configure_main()[source]

Configuration is the first phase of the build.

This writes the project TCL files and Makefile. It first collects all sources, IPs and constraints and then writes them to the TCL file along with the build steps.

src_file_filter(f)[source]
tool_options = {'lists': {'goals': 'String', 'rule_parameters': 'String', 'spyglass_options': 'String'}, 'members': {'methodology': 'String'}}
tool_options_defaults = {'goals': ['lint/lint_rtl'], 'methodology': 'GuideWare/latest/block/rtl_handoff', 'rule_parameters': [], 'spyglass_options': []}

edalize.trellis module

class edalize.trellis.Trellis(edam=None, work_root=None, eda_api=None, verbose=True)[source]

Bases: Edatool

argtypes = ['vlogdefine', 'vlogparam']
configure_main()[source]
classmethod get_doc(api_ver)[source]

edalize.vcs module

class edalize.vcs.Vcs(edam=None, work_root=None, eda_api=None, verbose=True)[source]

Bases: Edatool

argtypes = ['plusarg', 'vlogdefine', 'vlogparam']
configure_main()[source]
run_main()[source]
tool_options = {'lists': {'run_options': 'String', 'vcs_options': 'String'}}

edalize.verilator module

class edalize.verilator.Verilator(edam=None, work_root=None, eda_api=None, verbose=True)[source]

Bases: Edatool

argtypes = ['cmdlinearg', 'plusarg', 'vlogdefine', 'vlogparam']
build_main()[source]
check_managed_parser()[source]
configure_main()[source]
classmethod get_doc(api_ver)[source]
run_main()[source]

edalize.vivado module

class edalize.vivado.Vivado(edam=None, work_root=None, eda_api=None, verbose=True)[source]

Bases: Edatool

Vivado Backend.

A core (usually the system core) can add the following files:

  • Standard design sources

  • Constraints: Supply xdc files with file_type=xdc or unmanaged constraints with file_type SDC

  • IP: Supply the IP core xci file with file_type=xci and other files (like .prj) as file_type=user

argtypes = ['vlogdefine', 'vlogparam', 'generic']
build_main()[source]
build_post()[source]
build_pre()[source]
configure_main()[source]
classmethod get_doc(api_ver)[source]
run_main()[source]

Program the FPGA.

For programming the FPGA a vivado tcl script is written that searches for the correct FPGA board and then downloads the bitstream. The tcl script is then executed in Vivado’s batch mode.

edalize.vunit module

class edalize.vunit.Vunit(edam=None, work_root=None, eda_api=None, verbose=True)[source]

Bases: Edatool

argtypes = ['cmdlinearg']
build_main()[source]
configure_main()[source]
classmethod get_doc(api_ver)[source]
get_vunit_runner_path(src_files)[source]
run_main()[source]
src_file_filter(f)[source]
src_file_vhdl_standard_filter(f)[source]
testrunner = 'run.py'
testrunner_template = 'run.py.j2'

edalize.vunit_hooks module

This module exports VUnitHooks which can be used to implement advanced VUnit test cases.

class edalize.vunit_hooks.VUnitHooks[source]

Bases: object

Derive the VUnitRunner instance from this class and override its member functions if necessary.

create()[source]

Override this function to specify custom instantiation of VUnit.

Return type

VUnit

handle_library(logical_name, vu_lib)[source]

Override this to customize each library, e.g. with additional simulator options.

main(vu)[source]

Override this for final parametrization of the VUnit instance, or for custom invocation of VUnit.

class edalize.vunit_hooks.VUnitRunner[source]

Bases: VUnitHooks

The default runner which will be used if no vunit_runner.py is specified.

edalize.xcelium module

class edalize.xcelium.Xcelium(edam=None, work_root=None, eda_api=None, verbose=True)[source]

Bases: Edatool

argtypes = ['plusarg', 'vlogdefine', 'vlogparam', 'generic']
configure_main()[source]
classmethod get_doc(api_ver)[source]
run_main()[source]

edalize.xsim module

class edalize.xsim.Xsim(edam=None, work_root=None, eda_api=None, verbose=True)[source]

Bases: Edatool

CONFIG_MK_TEMPLATE = '#Auto generated by Edalize\nTARGET        = {target}\nTOPLEVEL      = {toplevel}\n\nVLOG_DEFINES  = {vlog_defines}\nVLOG_INCLUDES = {vlog_includes}\nGEN_PARAMS    = {gen_params}\n\nXELAB_OPTIONS =\t{xelab_options}\nXSIM_OPTIONS  = {xsim_options}\n'
MAKEFILE_TEMPLATE = '#Auto generated by Edalize\ninclude config.mk\n\nall: xsim.dir/$(TARGET)/xsimk\n\nxsim.dir/$(TARGET)/xsimk:\n\txelab $(TOPLEVEL) -prj $(TARGET).prj -snapshot $(TARGET) $(VLOG_DEFINES) $(VLOG_INCLUDES) $(GEN_PARAMS) $(XELAB_OPTIONS)\n\nrun: xsim.dir/$(TARGET)/xsimk\n\txsim -R $(XSIM_OPTIONS) $(TARGET) $(EXTRA_OPTIONS)\n\nrun-gui: xsim.dir/$(TARGET)/xsimk\n\txsim --gui $(XSIM_OPTIONS) $(TARGET) $(EXTRA_OPTIONS)\n'
argtypes = ['plusarg', 'vlogdefine', 'vlogparam', 'generic']
configure_main()[source]
classmethod get_doc(api_ver)[source]
run_main()[source]

edalize.reporting module

edalize.vivado_reporting module

edalize.quartus_reporting module

edalize.ise_reporting module

edalize.design_compiler module

class edalize.design_compiler.Design_compiler(edam=None, work_root=None, eda_api=None, verbose=True)[source]

Bases: Edatool

argtypes = ['vlogdefine', 'vlogparam', 'generic']
build_main()[source]
configure_main()[source]
classmethod get_doc(api_ver)[source]
src_file_filter(f)[source]
edalize.design_compiler.logger = <Logger edalize.design_compiler (WARNING)>

design-compiler Backend

A core (usually the system core) can add the following files:

  • Standard design sources

  • Libraries

Module contents