edalize package¶
Submodules¶
edalize.edatool module¶
- class edalize.edatool.Edatool(edam=None, work_root=None, eda_api=None, verbose=True)[source]¶
Bases:
object
- class edalize.edatool.FileAction(option_strings, dest, nargs=None, const=None, default=None, type=None, choices=None, required=False, help=None, metavar=None)[source]¶
Bases:
Action
- edalize.edatool.jinja_filter_param_value_str(value, str_quote_style='', bool_is_str=False)[source]¶
Convert a parameter value to string suitable to be passed to an EDA tool.
Rules:
Booleans are represented as 0/1 or “true”/”false” depending on the bool_is_str argument
Strings are either passed through or enclosed in the characters specified in str_quote_style (e.g. ‘”’ or ‘"’)
Everything else (including int, float, etc.) are converted using the str() function.
edalize.ghdl module¶
edalize.icarus module¶
edalize.icestorm module¶
edalize.ise module¶
- class edalize.ise.Ise(edam=None, work_root=None, eda_api=None, verbose=True)[source]¶
Bases:
Edatool
- MAKEFILE_TEMPLATE = '#Auto generated by Edalize\ninclude config.mk\n\nall: $(TOPLEVEL).bit\n\n$(TOPLEVEL).bit: $(NAME)_run.tcl $(NAME).xise\n\t$(EDALIZE_LAUNCHER) xtclsh $^\n\n$(NAME).xise: $(NAME).tcl\n\t$(EDALIZE_LAUNCHER) xtclsh $<\n'¶
- PGM_FILE_TEMPLATE = '\n# Batch script for programming the device using a JTAG interface.\n# Used with:\n# $ impact -batch {pgm_file}\n\nsetMode -bscan\nsetCable -port auto\nidentify\nassignFile -p {board_device_index} -file {bit_file}\nprogram -p {board_device_index}\nsaveCDF -file {cdf_file}\nquit\n'¶
- TCL_FILE_TEMPLATE = '#Auto generated by Edalize\nproc project_new_exist_ok name {{\n if {{ [catch {{ project new $name }}] }} {{\n project open $name\n }}\n}}\n\nproc xfile_add_exist_ok name {{\n if {{ [catch {{ xfile get [file tail $name] name }}] }} {{\n xfile add $name\n }}\n}}\n\nproject_new_exist_ok {design}\nproject set family "{family}"\nproject set device {device}\nproject set package {package}\nproject set speed {speed}\nproject set "Generate Detailed MAP Report" true\n'¶
- TCL_RUN_FILE_TEMPLATE = '#Auto generated by Edalize\nproject open $::argv\nprocess run "Generate Programming File"\n'¶
- argtypes = ['vlogdefine', 'vlogparam', 'generic']¶
edalize.isim module¶
- class edalize.isim.Isim(edam=None, work_root=None, eda_api=None, verbose=True)[source]¶
Bases:
Edatool
- CONFIG_MK_TEMPLATE = '#Auto generated by Edalize\nTARGET = {target}\nTOPLEVEL = {toplevel}\n\nVLOG_DEFINES = {vlog_defines}\nVLOG_INCLUDES = {vlog_includes}\nVLOG_PARAMS = {vlog_params}\n\nFUSE_OPTIONS =\t{fuse_options}\nISIM_OPTIONS =\t{isim_options}\n\nEXTRA_OPTIONS ?= {extra_options}\n'¶
- MAKEFILE_TEMPLATE = '#Auto generated by Edalize\ninclude config.mk\n\nall: $(TARGET)\n\n$(TARGET):\n\tfuse $(TOPLEVEL) -prj $(TARGET).prj -o $(TARGET) $(VLOG_DEFINES) $(VLOG_INCLUDES) $(VLOG_PARAMS) $(FUSE_OPTIONS)\n\nrun: $(TARGET)\n\t./$(TARGET) -tclbatch run_$(TARGET).tcl $(ISIM_OPTIONS) $(EXTRA_OPTIONS)\n\nrun-gui: $(TARGET)\n\t./$(TARGET) -gui $(ISIM_OPTIONS) $(EXTRA_OPTIONS)\n'¶
- RUN_TCL_TEMPLATE = '#Auto generated by Edalize\nwave log -r /\nrun all\nquit\n'¶
- argtypes = ['plusarg', 'vlogdefine', 'vlogparam']¶
edalize.modelsim module¶
edalize.openfpga module¶
- class edalize.openfpga.Openfpga(edam=None, work_root=None, eda_api=None, verbose=False)[source]¶
Bases:
Edatool
This calls the parent constructor, but also identifies whether the current system has correctly set the following environment variables:
OPENFPGA_PATH
: directory of the OpenFPGA framework, available here: https://github.com/lnis-uofu/OpenFPGASOFA_PATH
: directory of the SOFA eFPGA IPs, available here: https://github.com/lnis-uofu/SOFA
- argtypes = ['plusarg', 'vlogdefine', 'vlogparam']¶
- configure_main()[source]¶
Configuration is the first phase of the build.
This writes an OpenFPGA task file for SOFA/SOFA+ architectures, which will generate the according OpenFPGA flow. It first collects all verilog sources, top_module and then writes them into the task file.
Note: OpenFPGA flow may uses Yosys/VPR backend for Synthesis and P&R, respectively.
- edalize.openfpga.logger = <Logger edalize.openfpga (WARNING)>¶
OpenFPGA Flow Backend.
A core (usually the system core) can add the following files:
Benchmark RTL sources (Yosys supports only Verilog file type) and module name
The target FPGA architecture name, made with OpenFPGA fabric flow (SOFA,…)
Source the required environment variables: OPENFPGA_PATH, SOFA_PATH
Optional parameters: task options (’–debug’, …)
edalize.quartus module¶
- class edalize.quartus.Quartus(edam=None, work_root=None, eda_api=None, verbose=False)[source]¶
Bases:
Edatool
Initial setup of the class.
This calls the parent constructor, but also identifies whether the current system is using a Standard or Pro edition of Quartus.
- argtypes = ['vlogdefine', 'vlogparam', 'generic']¶
- configure_main()[source]¶
Configuration is the first phase of the build.
This writes the project TCL files and Makefile. It first collects all sources, IPs and constraints and then writes them to the TCL file along with the build steps.
- isPro = False¶
- makefile_template = {False: 'quartus-std-makefile.j2', True: 'quartus-pro-makefile.j2'}¶
edalize.rivierapro module¶
edalize.symbiyosys module¶
edalize.spyglass module¶
- class edalize.spyglass.Spyglass(edam=None, work_root=None, eda_api=None, verbose=True)[source]¶
Bases:
Edatool
- argtypes = ['vlogdefine', 'vlogparam']¶
- configure_main()[source]¶
Configuration is the first phase of the build.
This writes the project TCL files and Makefile. It first collects all sources, IPs and constraints and then writes them to the TCL file along with the build steps.
- tool_options = {'lists': {'goals': 'String', 'rule_parameters': 'String', 'spyglass_options': 'String'}, 'members': {'methodology': 'String'}}¶
- tool_options_defaults = {'goals': ['lint/lint_rtl'], 'methodology': 'GuideWare/latest/block/rtl_handoff', 'rule_parameters': [], 'spyglass_options': []}¶
edalize.trellis module¶
edalize.vcs module¶
edalize.verilator module¶
edalize.vivado module¶
- class edalize.vivado.Vivado(edam=None, work_root=None, eda_api=None, verbose=True)[source]¶
Bases:
Edatool
Vivado Backend.
A core (usually the system core) can add the following files:
Standard design sources
Constraints: Supply xdc files with file_type=xdc or unmanaged constraints with file_type SDC
IP: Supply the IP core xci file with file_type=xci and other files (like .prj) as file_type=user
- argtypes = ['vlogdefine', 'vlogparam', 'generic']¶
edalize.vunit module¶
edalize.vunit_hooks module¶
This module exports VUnitHooks
which can be used to implement advanced VUnit test cases.
- class edalize.vunit_hooks.VUnitHooks[source]¶
Bases:
object
Derive the
VUnitRunner
instance from this class and override its member functions if necessary.
- class edalize.vunit_hooks.VUnitRunner[source]¶
Bases:
VUnitHooks
The default runner which will be used if no
vunit_runner.py
is specified.
edalize.xcelium module¶
edalize.xsim module¶
- class edalize.xsim.Xsim(edam=None, work_root=None, eda_api=None, verbose=True)[source]¶
Bases:
Edatool
- CONFIG_MK_TEMPLATE = '#Auto generated by Edalize\nTARGET = {target}\nTOPLEVEL = {toplevel}\n\nVLOG_DEFINES = {vlog_defines}\nVLOG_INCLUDES = {vlog_includes}\nGEN_PARAMS = {gen_params}\n\nXELAB_OPTIONS =\t{xelab_options}\nXSIM_OPTIONS = {xsim_options}\n'¶
- MAKEFILE_TEMPLATE = '#Auto generated by Edalize\ninclude config.mk\n\nall: xsim.dir/$(TARGET)/xsimk\n\nxsim.dir/$(TARGET)/xsimk:\n\txelab $(TOPLEVEL) -prj $(TARGET).prj -snapshot $(TARGET) $(VLOG_DEFINES) $(VLOG_INCLUDES) $(GEN_PARAMS) $(XELAB_OPTIONS)\n\nrun: xsim.dir/$(TARGET)/xsimk\n\txsim -R $(XSIM_OPTIONS) $(TARGET) $(EXTRA_OPTIONS)\n\nrun-gui: xsim.dir/$(TARGET)/xsimk\n\txsim --gui $(XSIM_OPTIONS) $(TARGET) $(EXTRA_OPTIONS)\n'¶
- argtypes = ['plusarg', 'vlogdefine', 'vlogparam', 'generic']¶